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| Agilent N4850A DigRF v3 Acquisition Probe N4860A DigRF v3 Stimulus Probe Data Sheet Evaluate and integrate your DigRF v3 components more easily DigRF v3 Challenges The DigRF v3 standard presents new challenges for mobile wireless development, integration and validation teams as the communications link between the BB-ICs and the RF-ICs evolve from analog to digital. Digital IQ data and control information are transferred between the BB-IC and the RF-IC over the DigRF v3 interface. Engineers traditionally use spectrum analyzers to evaluate the analog interface between the BB-IC and the RF-IC, but now they need new tools because spectrum analyzers are incapable of measuring the DigRF v3 digital serial interface. RF-IC development teams must verify operation of the RF-IC before the start of the handset integration phase. Spectrum analyzers and signal sources are no longer sufficient for characterizing the new generation of RF-ICs that comply to the DigRF v3 standard. To validate RF-IC operation, engineering teams need DigRF v3 digital serial stimulus and analysis tools that operate in concert with the traditional RF tools. The challenges for BB-IC validation teams mirrors that of the RF-IC teams, as the signal sources and spectrum analyzers must be replaced by DigRF v3 digital serial stimulus and analysis tools to validate BB-IC functionality. Figure 1. N4850A DigRF v3 acquistion probe Meeting the DigRF v3 Challenges The Agilent Technologies N4850A acquisition probe and the N4860A stimulus probe operate in conjunction with Agilent 16800 and 16900 Series serial logic analyzers to provide the digital serial stimulus and acquisition capabilities required to independently evaluate an RF-IC or BB-IC with a DigRF v3 interface or integrate your mobile wireless designs. Figure 2. N4860A DigRF v3 stimulus probe Introduction to DigRF v3 The DigRF v3 standard was designed to enable interoperability between RF-ICs and BB-ICs from different suppliers. Additional benefits include reduced cost, higher bandwidth and extended battery life. The physical layer of the DigRF v3 interface consists of six signals (see Figure 3) with independent transmit and receive paths. Additional signals are specified for diversity mode. The DigRF v3 specification allows for 1.8 V LVDS, 1.2 V LVDS or SLVDS electrical interface voltages. The DigRF v3 interface transitions between high speed, low power and sleep modes dynamically. The DigRF v3 standard specifies data packets and control packets. Embedded in the data packets is the digital IQ representation of the RF signal. Control packets contain the configuration and status information necessary to keep the BB-IC and RF-IC operating in synchronization. SYSCLKEN SYSCLK BB-IC Txp Txn Rxp Rxn RF-IC Figure 3. DigRF v3 physical interconnect scheme 2 Test Scenarios RF-IC development teams, BB-IC development teams and integration teams each have unique test and measurement requirements as they validate their products, as shown in Figures 4a-4c. Integration measurement needs SYSCLKEN SYSCLK BB-IC Visibility port * * * * Txp Txn Rxp Rxn RF-IC Acquire Tx and Rx transactions Decode/view control packets Extract digital IQ (Rx and Tx) for vector signal analysis Monitor BB-IC internal operations Figure 4a. The integration team's measurement needs RF-IC evaluation measurement needs SYSCLKEN SYSCLK Txp Txn Rxp Rxn * Generate and drive control packets * Generate and drive digital IQ (Tx) * Acquire digital IQ (Rx) for vector signal analysis Figure 4b. Measurement needs for evaluating the RF-IC RF-IC BB-IC evaluation measurement needs SYSCLKEN SYSCLK C DSP Txp Txn Rxp Visibility port * * * * Decode and view control packets (Tx) Extract digital IQ (Tx) for vector signal analysis Generate and drive digital IQ (Rx) Monitor BB-IC internal operations Rxn Figure 4c. Measurement needs for evaluating the BB-IC 3 BB-IC/RF-IC Integration Figure 5 shows the equipment required to integrate the RF-IC with the BB-IC. A signal generator and spectrum analyzer provide stimulus/response capabilities in the RF domain. Traffic on the DigRF v3 link between the RF-IC and BB-IC is monitored by the N4850A acquisition probe. Control packets are viewed in the logic analyzer's packet viewer, and IQ data packets are analyzed using the Agilent 89601A vector signal analysis package. The logic analyzer monitors the BB-IC visibility port to help you gain insight into C and DSP and correlate these internal operations with traffic on the DigRF v3 interface. Visibility into the internal operation of the BB-IC can be achieved by monitoring the visibility port, which is designed into the BB-IC. Typically, you can track operation of the microcontroller and DSP through the visibility port. This allows you to analyze control flow, track internal processing of digital IQ and correlate BB-IC internal operations to DigRF v3 traffic. Signal generator BB-IC Visibility port RF-IC Spectrum analyzer Logic analyzer Figure 5. Test and measurement configuration for RF-IC BB-IC integration Figure 6. Decoder view of BB-IC internal operation 4 BB-IC/RF-IC Integration (continued) The N4850A acquisition probe captures transactions on the Tx and Rx paths of the DigRF v3 interface independently. Control packets are decoded and displayed on the logic analyzer's packet viewer as illustrated in Figure 7. These capabilities enable you to track the status and control flow of the system under test to identify defects and tune performance parameters. There is a two-step process for analyzing the digital IQ data packets that are acquired by the N4850A acquisition probe. Using the signal extractor tool, the headers and padding are removed, leaving the digital IQ representation of the RF signal. The IQ data then can be analyzed by the vector signal analysis package to evaluate EMV, sidebands and other critical RF parameters. This capability enables systems integrators to characterize RF-IC behavior and adjust DSP algorithms or the RF-IC configuration to optimize performance. Figure 7. Packet view of DigRF v3 control traffic Figure 8. Vector signal analysis of DigRF v3 digital IQ 5 RF-IC Evaluation Figure 9 shows a test and measurement configuration that will enable RF-IC designers to verify operation of their components with the DigRF v3 interface. Stimulus and analysis of the RF interface is provided by a signal generator and a spectrum analyzer. Serial digital acquisition and stimulus for the DigRF v3 interface are provided by the N4850A and N4860A operating under control of an Agilent 16800 or 16900 Series logic analyzer. With the ability to monitor and control the RF-IC through the DigRF v3 interface, validation engineers can evaluate transmitter and receiver behavior. Signal generator N4860A RF-IC Tx Rx Logic analyzer N4850A Spectrum analyzer Figure 9. Test equipment configuration to verify RF-IC operation 6 RF-IC Evaluation (continued) The logic analyzer enables you to specify the desired RF-IC configuration. The specified configuration is embedded into DigRF v3 control packets. The N4860A stimulus probe outputs DigRF v3-compliant control packets that configure the RF-IC. Digital IQ data can be loaded into the logic analyzer from a variety of sources, including Signal Studio and Advanced Design System (ADS). The logic analyzer embeds the IQ data in DigRF v3-compliant packets. The data packets are transferred to the RF-IC with the proper timing by the stimulus probe. The RF-IC processes the digital IQ data and generates an RF signal, which is characterized using a spectrum analyzer. Control packets, as specified by the user, can be inserted into the data packet flow while looping through the waveform. With this feature, you can make RF-IC configuration adjustments - like the gain setting of the RF amplifiers - interactively. Figure 10. Conversion of control bit into DigRF v3 packets Figure 11. Generation of digital IQ representation of RF signal 7 RF-IC Evaluation (continued) Using the logic analyzer and stimulus probe, the RF-IC can be configured to receive an RF signal. The RF signal source generates the RF waveform of interest. The RF-IC processes the waveform and generates a DigRF v3 serial bit stream with the resulting digital IQ data. The acquisition probe captures the DigRF v3 data packets generated by the RF-IC and extracts the digital IQ data for analysis using the vector signal analysis package. Figure 12. Vector signal analysis of digital IQ on the logic analyzer 8 BB-IC Evaluation Figure 13 shows the test and measurement configuration that will enable BB-IC designers to verify operation of their components with the DigRF v3 interface. Visibility into the internal operation of the BB-IC is acquired by the logic analyzer through the BB-IC visibility port. The acquisition probe enables the logic analyzer to monitor traffic on the DigRF v3 Tx path as generated by the BB-IC. The stimulus probe can be configured to generate control and digital IQ data packets for the BB-IC over the DigRF v3 Rx path. Validation engineers can use these capabilities to evaluate many of the critical blocks within the BB-IC. Visibility into the internal operation of the BB-IC can be achieved by monitoring the visibility port, which is designed into the BB-IC. Typically, you can track microcontroller and DSP operation through the visibility port. In this manner, control flow can be analyzed and internal processing of digital IQ can be tracked. Visibility port Rx C DSP Tx N4860A BB-IC N4850A Logic analyzer Figure 13. Test equipment configuration needed to verify BB-IC operation Figure 14. Decoder view of BB-IC internal operation 9 BB-IC Evaluation (continued) The N4850A acquisition probe captures the Tx traffic generated by the BB-IC. The control packets are identified by the logic analyzer, decoded and displayed on the logic analyzer using the packet viewer. Debug and validation of the configuration and control functions of the BB-IC/RF-IC interface are accelerated by using these capabilities. The N4850A acquisition probe captures the Tx traffic generated by the BB-IC. The data packets are identified and the digital IQ data is extracted from these packets using the signal extractor tool. The digital IQ data is analyzed by the 89601A vector signal analysis tools running on the logic analyzer. These capabilities enable BB-IC validation team to validate that the digital IQ was properly converted to DigRF v3 format. In addition, the DSP algorithms that generated the IQ can be evaluated. Figure 15. Protocol decode view of DigRF v3 control traffic Figure 16. Vector signal analysis of DigRF v3 digital IQ 10 BB-IC Evaluation (continued) Digital IQ data and control signals are formatted into DigRF v3-compliant packets on the logic analyzer. The N4860A stimulates the BB-IC with the specified data and control packets. In this manner, BB-IC validation teams can analyze how the BB-IC handles the breadth of status and control responses that an RF-IC could generate and how the BB-IC handles various digital IQ streams. Figure 17. Generation of digital IQ representation of RF signals using Signal Studio 11 Characteristics for N4850A DigRF v3 Digital Acquisition Probe Features Supports state analysis of DigRF v3 standard; 2.5G and 3GPP air standards - e.g. GSM, EDGE, CDMA, CDMA-2K, W-CDMA Maximum acquisition speed: 312 Mbps Benefits Validate and troubleshoot handsets and mobile wireless devices incorporating DigRF v3 across a wide variety of over-air standards Run at any DigRF v3-compliant operating mode (sleep, low, medium, high speed) with performance headroom Acquire traffic, no matter which DigRF v3-compliant voltage level you are using. Supports Voltage Level compliant with standard SysClk speed support: 19.2 MHz, 26.0 MHz, 38.4 MHz Tracks changes in speed modes Acquire 17 differential channels Acquire traffic, no matter which DigRF v3-compliant speed you are using Verify mode change algorithms real time with a single acquisition Simultaneously monitor a Tx/Rx bidirectional bus, even with Tx and Rx running at different bus modes Parallel format enables you to trigger on protocol-specific packets, specific bits within a packet (for example, control bits within a packet), and protocol violations - getting you to the root cause of a problem quicker. In addition, combine the parallel format with a logic analyzer that has deep acquisition memory to capture even more system activity, in both directions, for analysis and debug. Quickly analyze and debug DigRF v3 digital control and raw IQ data in an intuitive format. The packet viewer lets you operate at the packet level or view detailed information for each individual packet. Quickly identify the status of your system by just looking at the probe. DigRF v3 error detection includes: Tx/Rx * Detected data speed does not match requested speed * Unable to locate stable data; excessive jitter impacts data eye closure * Too little time between SysClk toggling to data toggling (time definition is user defined) Clock * Clock stopped in the middle of a frame * SysClk toggling when SysClkEN is false * Start-of-frame sync not found even though data is toggling Focus only on the data you want to see Converts serial bus stream to parallel format DigRF v3 protocol decoder and packet viewer LEDs: Two each for Tx, Rx, and CLK Tx: Speed and synchronization status Rx: Speed and synchronization status CLK: SysClk is enabled, disabled Select the specific Tx/Rx signals, control, and data information to be captured by the logic analyzer 12 Characteristics for N4850A DigRF v3 Digital Acquisition Probe (continued) Features Extract and transfer digital IQ generated from your over-air data to 89600 VSA software Connection port to N4860A digital stimulus probe Identifies invalid sync words so you can trigger on them with an external device, like an oscilloscope Supports up to 2048 bits for user-defined payload Stack or rack multiple N4850A acquisition or N4860A stimulus probes Configuration files Probe the device under test with a variety of differential probes: E5381A flying leads, E5387A or 5495A soft touch connectorless probes, or the E5379A Samtec probe Correlate DigRF v3 activity with microcontroller and DSP operation Benefits Rapidly work through scenarios that let you identify RF signal problems quickly and fine tune your DSP algorithm Perform comprehensive stimulus and acquisition testing Quickly identify faults in order to perform functional and parametric analysis around the fault condition The tools provide support for your custom data packets The small probe minimizes the footprint of test equipment next to the device under test Saves time and simplifies measurement setup The high-bandwidth E5381A differential flying leads provide the highest signal-quality measurement. In addition, probing flexibility allows you to use soft touch or Samtec probes. A correlated system view enables you to rapidly isolate defects and verify system operation 13 Characteristics for N4860A 312-Mbps Digital Stimulus Probe Features Pattern generator loop macros Maximum stimulus speed: 312 Mbps Benefits Provide continuous DigRF v3 stimulus to replace a missing DigRF v3-based BB-IC or RF-IC Run at any DigRF v3-compliant operating mode (sleep, low power or high speed) with performance headroom Generate DigRF v3 traffic, no matter which DigRF v3-compliant voltage level you are using Stimulus Voltage Level compliant with standard SysClk speed support: 26.0 MHz Connect to target via SMA connectors Modify critical control settings while looping (e.g. adjust RF-IC amplifier gain) Create digital control and data stimulus in a simple ASCII format using Signal Studio, Advanced Design System (ADS), a captured logic analyzer trace, or a custom programming package Convert raw IQ ASCII data and user-defined control information to DigRF v3-compliant data and control packets User specification of order and timing of control and data packets. Generate DigRF v3 traffic, no matter which DigRF v3-compliant speed you are using. Provide stimulus to compensate for a missing BB-IC or RF-IC See how your device or system responds without stopping the stimulus probe to change control settings Use your tool of choice to generate your stimulus data Automation saves time and eliminate errors Evaluate the DUT under a variety of control configurations, data patterns, and timing sequences. NOTE: Stimulus order and timing of control and data packets is determined when the N4860A is set up. Order and timing of data and control packets is NOT altered in response to the "Clear To Send" when stimulating the RF-IC. 14 N4850A and N4860A Physical Characteristics Dimensions 269.48 (10.609) 56.91 (2.240) Dimensions: mm/(inch) 312Mbps DIGITAL ACQUISITION PROBE N4850A Figure 18. N4850A exterior dimensions SMA connectors. Refer to Users Guide or online help On/Off Power switch Agilent Technologies Status LEDs Cable for connecting to device under test Logic analyzer connection via Samtec probes N4850A 312Mbps DIGITAL ACQUISITION PROBE S1 S0 DATA CLOCK 3.3V Max CTS TX RX CLK See Users Guide or online help for channel/signal assignments DC Power Option connector to N4860A Figure 19. N4850A front panel, rear panel, and top view Agilent Technologies S1 S0 Folded cable length is approx. 15" Unfolded cable length is approx. 48" DATA CLOCK 3.3V Max CTS TX 247.65 (9.750) RX CLK See Users Guide or online help for channel/signal assignments 15 N4850A and N4860A Physical Characteristics (continued) Dimensions 55.98 (2.204) 269.48 (10.609) Dimensions: mm/(inch) S1 3.3V Max S0 DATA CLOCK CTS TX RX CLK TxDataP TxDataN See Users Guide or online help for signal assignments RxDataP RxDataN SysClk SysClkEn Figure 20. N4860A exterior dimensions SMA connectors. Refer to Users Guide or online help On/Off Power switch N4860A Figure 21. N4860A front panel, rear panel, and top view N4860A 312Mbps DIGITAL RF STIMULUS PROBE 247.65 (9.750) Connectors for pattern generator Status LEDs SMA connectors. Refer to Users Guide or online help 312Mbps DIGITAL RF STIMULUS PROBE S1 S0 3.3V Max DATA CLOCK CTS TX RX CLK TxDataP TxDataN RxDataP RxDataN SysClk SysClkEn See Users Guide or online help for signal assignments DC Power Option connector to N4850A Power 12 V and 5 A (60 W) max Weight Max net Max shipping 2.0 kg (4.4 lbs) 4.5 kg (10.0 lbs) Instrument operating environment Temperature Altitude Humidity 16 0 C to 55 C ( 32 F to 131 F) To 3000 m (10,000 ft) 8 to 80% relative humidity at 40 C (104 F) Ordering Information When you configure your DigRF v3 measurement system,consider the following: 1. Ability to provide DigRF v3 stimulus: For comprehensive stimulus and response testing of your DigRF v3 device or system, select a logic analyzer with digital pattern generation capability (16822A, 16823A, or a 16900 modular logic analysis system with a 16720A pattern generator module). 2. Flexibility to grow as your measurement needs evolve: A modular 16900 Series logic analyzer addresses your measurement needs today and allows you to grow as your needs evolve. 3. Modification of the logic analyzer's DigRF v3 protocol decoder: The DigRF v3 standard provides the flexibility to customize your control structure and data packets for your specific application. With the B4641A protocol development kit, you can modify the logic analyer's DigRF v3 protocol decoder to track your custom solution. Target design and test equipment requirements for DigRF v3 digital acquisition and stimulus measurements In addition to compatible measurement equipment, the device under test (DUT) requires the following to ensure proper acquisition and stimulus of the DUT. DUT requirements for the N4850A acquisition probe: * Access to SysClk to determine when data is valid on the serial bus * Probing connection for the acquisition probe, preferably at the receiver. Please refer to the N4850A User Guide and the Agilent N4850A Design Guide (N4850-97002) for information on designing a connection with good signal integrity. DUT requirements for use with N4860A stimulus probe: * SMA (m-m) connectors on the target. The number of SMA connectors depends on your test scenario: BB-IC turn on, RF-IC validation, or system integration * Place a 50-ohm termination resistor between the positive and negative differential pair 17 Ordering Information (continued) To configure a complete DigRF v3 digital acquisition and stimulus system, you will need to order or have the following items: Pattern generator cables 1 N4860A probe, SMA cables required for target connection 5 Samtec probes 3 Logic analyzer 1 N4850A probe 4 Differential flying lead probe DigRF v3 digital acquisition and stimulus system Probes between the N4850A and the... 1. DigRF v3 probes1 (One each per Tx/Rx pair) 2. Method to create IQ data 3. Logic analyzer with 48-channel pattern generator2 4. Device under test (One of the following for each N4850A) 5. Logic analyzer (Two Samtec probes per N4850A - one for Tx and one for Rx. Select probe that is compatible with your logic analyzer) * E5385A for logic analyzers with a 40-pin cable connection (16822A, 16823A, 16910/11A) * E5378A for logic analyzers with a 90-pin cable connection (1695X modules) N4860A 312 Mbps digital stimulus probe * N4860A-040: Set of four 40 inch SMA cables N4850A 312 Mbps digital acquisition probe * -010 for node-locked license * -020 for floating (server) license 1 2 * Signal Studio * ADS * Convert captured logic analyzer trace to stimulus * Custom programmatic generation 16800 Series portables * 16822A - 68 ch * 16823A - 102 ch 16900 Series modular mainframe with at least one each of the following: * 16900 Series module(s) * 16720A pattern generator module * E5381A differential flying lead probe * E5405A differential pro series soft touch probe * E5387A differential soft touch probe * E5379A differential Samtec probe N4860A digital stimulus probe requires an N4850A digital acquisition probe to operate Compatible with 16800 or 16900 Series logic analyzers with 68 channels or more. Diversity mode requires use of a 16900 modular system with one 68-channel (or more) logic analyzer module for each Tx/Rx pair. 18 Ordering Information (continued) To configure a complete DigRF v3 digital acquisition system, you will need to order or have the following items: 4 Samtec probes 3 Logic analyzer 1 N4850A probe 3 Differential flying lead probe DigRF v3 digital acquisition system Probes between the N4850A and the... 1. DigRF v3 probes (One per Tx/Rx pair) 2. Logic analyzer1 3. Device under test (One of the following for each N4850A) 4. Logic analyzer (Two Samtec probes per N4850A - one for Tx and one for Rx. Select probe that is compatible with your logic analyzer) * E5385A Samtec probe for logic analyzers with a 40-pin cable connection (16800 Series, 16910/11A) * E5378A Samtec probe for logic analyzers with a 90-pin cable connection (1695X modules) N4850A 312-Mbps digital acquisition probe * -010 for node-locked license * -020 for floating (server) license 16800 Series portables * 16802A - 68 ch * 16803A - 102 ch * 16804A - 136 ch * 16806A - 204 ch * 16822A - 68 ch * 16823A - 102 ch 16900 Series modular mainframe with at least one 16900 Series module * E5381A differential flying lead probe * E5405A differential pro series soft touch probe * E5387A differential soft touch probe * E5379A differential Samtec probe 1 Compatible with 16800 or 16900 Series logic analyzers with 68 channels or more 19 www.agilent.com Agilent Email Updates www.agilent.com/find/emailupdates Get the latest information on the products and applications you select. Remove all doubt Our repair and calibration services will get your equipment back to you, performing like new, when promised. You will get full value out of your Agilent equipment throughout its lifetime. Your equipment will be serviced by Agilenttrained technicians using the latest factory calibration procedures, automated repair diagnostics and genuine parts. You will always have the utmost confidence in your measurements. Agilent offers a wide range of additional expert test and measurement services for your equipment, including initial start-up assistance, onsite education and training, as well as design, system integration, and project management. For more information on repair and calibration services, go to: www.agilent.com/find/removealldoubt For more information on Agilent Technologies' products, applications or services, please contact your local Agilent office. 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Related literature Publication title Agilent 16800 Series Portable Logic Analyzers Agilent 16900 Series Logic Analysis Mainframes Probing Solutions for Agilent Technologies Logic Analyzers Publication type Data sheet Data sheet Catalog Publication number 5989-5063EN 5989-0421EN 5968-4632E 1890 924 204 972-3-9288-504/544 39 02 92 60 8484 31 (0) 20 547 2111 34 (91) 631 3300 0200-88 22 55 (French) 44 (21) 8113811 (Opt 2) Switzerland (German) 0800 80 53 53 (Opt 1) United Kingdom 44 (0) 118 9276201 Other European countries: www.agilent.com/find/contactus Revised: October 24, 2007 Ireland Israel Italy Netherlands Spain Sweden Switzerland Product Web site For the most up-to-date and complete application and product information, please visit our product Web site at: www.agilent.com/find/DigRF Product specifications and descriptions in this document subject to change without notice. (c) Agilent Technologies, Inc. 2007 Printed in USA, December 6, 2007 5989-6058EN www.agilent.com/find/DigRF |
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